1. Field of the Invention
This invention relates in general to integrated circuit design.
2. Description of the Related Art
In the design of integrated circuits, models such as e.g. Register Transfer Language (RTL) models are written by logic designers for describing the functionality of design blocks. The sub-component RTL models are integrated into a complete RTL model of an integrated circuit that is simulated to establish correct functionality. The RTL models serve as specifications for refining each sub-component of the design into transistor level circuit models—be it synthesized or custom designed. Once the RTL model and circuit implementation (e.g. transistor level circuit model) of a sub-component are available, the RTL model is proved equivalent to the circuit implementation using standard equivalence checking technology. This equivalence checking may be necessary for all sub-components that make up the integrated circuit because the RTL model and its simulation semantics may be required to be predictive of silicon behavior.
Ideally, equivalence checking between the RTL model and the circuit implementation of sub-components should be achievable even when no assumptions are made on the sub-component primary inputs i.e., they are left completely non-deterministic. In most cases, this is not possible as the logic and/or underlying circuit implementation of the sub-components are designed to work correctly only under a restricted environment. Therefore, assumptions that constrain the behavior of a sub-components primary inputs are necessary in order to establish equivalence between each sub-component RTL and the corresponding circuit implementation. This implies that the circuit implementation is equivalent to the RTL model only for a subset of the reachable state space, i.e. the circuit's environment must satisfy the assumptions made during equivalence checking.
In a typical design verification flow, there are a number of user constraints that have been used in the subcomponent's equivalence checking flow. User constraints are assumptions about the environment of the block under test that a user (designer) specifies. These constraints can be treated as assertions that must be satisfied in the context of the full integrated circuit environment. These assertions may be expressed as Boolean conditions that must always hold during all modes of operation of the integrated circuit. A methodology to check the correctness of these assertions and to ensure the absence of over-constraining is important for finding bugs due to incorrect/over-constrained equivalence checking at the sub-component level.
One often-used method of assertion checking is to write simulation monitors to monitor assertion violations every simulation cycle using directed test suites and functional test vectors. The problem with such a method lies in the difficulty in generating directed test vectors, and their inherent incompleteness from the point of view of coverage. The simulation sequence used may not “hit” the bug, which may then go undetected. Also, simulation monitors usually have an adverse effect on simulation performance.
What is needed is an improved technique for integrated circuit design.
The use of the same reference symbols in different drawings indicates identical items unless otherwise noted.